This application claims priority to Korean Patent Application No. 2002-35883, filed on Jun. 26, 2002, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices having power circuits therein.
Integrated circuit (semiconductor) devices continue to be developed so as to increase their capacity and speed and/or to lower their power consumption. The internal memory cell array power supply voltage is a voltage that is typically reduced from an external power supply voltage to lower device power consumption. When the internal memory cell array power supply voltage is reduced, the operational characteristics of the device, such as the performance of the bit-line sense amplifiers, may be degraded.
One approach to providing a reduced voltage internal power supply is to provide a down converter to drop the external power supply voltage from a relatively high level to a substantially constant level to generate an internal power supply voltage for the integrated circuit device, such as an integrated circuit memory device. For example, in an integrated circuit memory device such as a dynamic random access memory (DRAM) or the like, an internal voltage down converter is typically provided for converting an external power supply voltage to supply a substantially constant internal power supply voltage to internal circuits, such as memory cell arrays. An example of an memory device with a down converter that generates an internal supply voltage for sensing and amplifying the potential of a bit line connected to a memory cell is generally illustrated in FIG. 1. As shown in FIG. 1, the circuit includes a reference voltage generator 10 that generates a reference voltage VREFA and a cell array voltage generator 21. The cell array voltage generator 21 compares the reference voltage VREFA with a cell array internal voltage AIVC generated by the cell array voltage generator 21 based on the reference voltage VREFA. The cell array voltage generator 21 driver stage is typically constructed with a reference voltage comparator circuit provided by current mirror type differential amplifiers and with a driver circuit that may include P-type MOS transistors.
As further illustrated in FIG. 1, the memory device has a first power supply voltage VDD and first ground voltage VSS that are respectively provided to the reference voltage generator 10 and the cell array voltage generator 21 through a first power supply line 11 and a first ground line 12. In addition, a second power supply voltage VDDQ and second ground voltage VSSQ are respectively provided to the output buffers 80, 90 through a second power supply line 81 and a second ground line 82. As shown in FIG. 1, the reference voltage generator 10 and the cell array voltage generator 21 are provided as a peripheral circuit (relative to the memory cell arrays 60, 70) of the integrated circuit memory device.
Thus, the integrated circuit memory device illustrated in FIG. 1 includes separate external power supply voltage sources for driving the memory cell array and sense amplifier blocks 60, 70 and the output buffers 80, 90. Provision of such separate power supplies may improve an output driving function of the output data DOUT1, DOUT2 from the device and may further reduce or even eliminate interference between ones of the power supplies resulting from noise generated by the other power supply. As shown in FIG. 1, the first power supply voltage VDD is used to power the reference voltage generator 10 and the cell array voltage generator 21, which circuits generate the cell array internal voltage AIVC. The second power supply voltage VDDQ is applied as the external power supply voltage for the output buffers 80, 90. The voltage level of the second power supply voltage VDDQ may be the same or a different level than the first power supply voltage VDD.
The cell array internal voltage AIVC is supplied on line L1 to the memory cell array and sense amplifier blocks 60, 70 through the driving PMOS transistors 40, 50. Cell data output from the memory cell array and sense amplifier blocks 60, 70 is provided to the output buffers 80, 90 and is output as output data DOUT1, DOUT2. However, as the cell array internal voltage AIVC is generated based on the first power supply voltage VDD while the second power supply voltage VDDQ is used for the output buffers 80, 90, various problems may result. For example, as the amount of power consumed by the reference voltage generator 10 and the cell array voltage generator 21 may be relatively high, the power consumption of an overall chip may be undesirably increased. As the number of associated memory cell arrays and memory banks is increased, power consumption will also generally increase. In addition, bit line sensing speed may be limited as a result of the turn-on resistance characteristics of the P-type MOS transistors in the cell array voltage generator 21 that generates the voltage AIVC used in bit line sensing. When the bit line sensing speed slows, active restore operations may also deteriorate and various memory performance parameters, such as, RAS active command to CAS active command delay time (wherein xe2x80x9cCAS activexe2x80x9d refers to Read or Write command) for securing Bit Line Sensing time (tRCD), RAS Precharge time (i.e., the delay time between a RAS Precharge command and a next RAS active command) for securing Bit line equalize time (tRP) and RAS active time (i.e., the delay time from a RAS active command to a RAS Precharge command) for securing a Bit line sensing time and a cell restore time (tRAS), may be impacted or the operating margin for the memory device may become tighter.
Furthermore, as the first power supply voltage VDD is generally applied to the peripheral voltage generation circuit and, as the internal voltage AIVC to the core memory cell arrays, through a VDD pad, the cell array power supply and the peripheral circuit power supply are not isolated from each other. In other words, as no pad separation is provided between the cell array power supply and the peripheral circuit power supply, noise occurring in the cell array power supply may also affect the peripheral voltage generation circuit. If the peripheral circuit is affected by the noise, the reliability of the integrated circuit memory device may deteriorate.
More particularly, the first and second power supply lines 11, 81 and the first and second ground lines 12, 82 shown in FIG. 1 are typically formed from metal wires through a semiconductor fabricating process, and the metal wires are connected with the package exterior of the memory device on corresponding pins through corresponding pads. Therefore, the power supply noise may result from an inductance and a resistance component in the power supply line and the ground line. Such power supply noise can generally be divided into a power supply voltage noise and a ground noise, which are generally present during a restoring operation and/or a data output operation. For the restore operation, the power supply voltage noise may result from a voltage level increase towards the power supply voltage VDD in a bit line B/L, and the ground noise may result from discharge to the ground voltage VSS in an inverted bit line B/LB. In the case of the data output operation, the power supply noise may be caused by an external load circuit driven by the data output. Thus, the external resistance may cause a voltage drop that may reduce the voltage level applied not only to the peripheral circuits but also to the memory cell array and sense amplifier blocks 60, 70.
In addition, for the conventional integrated circuit memory device of FIG. 1, when a word line is driven or a sense amplifier is enabled, a relatively large current flow may momentarily occur, which may cause a drop in the level of the internal power supply voltage. In other words, such a current consumption in a final driver stage of the internal voltage down converter may adversely affect the mean operating current. Accordingly, the circuit of FIG. 1 may suffer from an undesirable level of power consumption and various other operational reliability problems.
Methods according to embodiments of the present invention provide for operation of integrated circuit devices. A power supply terminal of a memory cell array and a sense amplifier of the integrated circuit device are driven with a selected one of a first power supply voltage or a second power supply voltage responsive to a control signal. The second power supply voltage is delivered to the integrated circuit device separate from the first power supply voltage. More particularly, the power supply terminal may be a power supply terminal of a differential sense amplifier.
In some embodiments of the present invention, the first power supply voltage is an internal voltage generated by an internal voltage generator circuit of the integrated circuit device. The internal voltage generator circuit is powered by an external power supply voltage separate from the second power supply voltage. A power supply of a data output circuit of the integrated circuit may also be driven with the second power supply voltage. The level of the first power supply voltage may be at least equal to the level of the second power supply voltage. In various embodiments, the level of the first power supply voltage about equals the level of the second power supply voltage. The control signal may be an external control signal, such as a mode register set command.
In further embodiments of the present invention, integrated circuit devices are provided including a control circuit that drives a power supply terminal of a memory cell array and a sense amplifier of the integrated circuit device with a selected one of a first power supply voltage or a second power supply voltage responsive to a control signal. The second power supply voltage is delivered to the integrated circuit device separate from the first power supply voltage. The integrated circuit device may further include an internal voltage generator circuit powered by an external power supply voltage separate from the second power supply voltage, and the first power supply voltage may be an internal voltage generated by the internal voltage generator circuit. In addition, the integrated circuit device may include a data output circuit that is powered by the second power supply voltage.
In other embodiments of the present invention, the integrated circuit device includes a switch circuit that couples the second power supply voltage to the power supply terminal. The switch circuit may be a PMOS transistor and the control signal may be coupled to a gate of the PMOS transistor. The internal voltage generator circuit may also include a switch circuit that couples the internal voltage to the power supply terminal. In particular embodiments of the present invention, the internal voltage generator circuit includes a driver transistor that outputs the internal voltage and the switch circuit of the internal voltage generator includes a PMOS transistor that couples the first power supply voltage to a gate of the driver transistor.
In further embodiments of the present invention, integrated circuit memory devices are provided including a sense amplifier having first and second inputs electrically coupled to a pair of differential signal lines. A memory cell array is coupled to the sense amplifier. A voltage generator circuit is provided having an internal voltage output that is selectively coupled to one of the pair of differential signal lines. The voltage generator circuit is powered by a first power supply voltage. A second power supply voltage is selectively coupled to the one of the pair of differential signal lines. The second power supply voltage is delivered to the integrated circuit memory device separate from the external power supply voltage. A control circuit selects the internal voltage output or the second power supply voltage responsive to a control signal.
In other embodiments of the present invention, methods are provided for supplying power supply voltage in a semiconductor memory device. A second power supply voltage, applied from external to the semiconductor memory device separately from a first power supply voltage, is applied to a data output circuit. The second power supply voltage is directly supplied to a memory cell array and sense amplifier circuit as a cell array internal voltage for operation of the memory cell array and sense amplifier. The second power supply voltage maybe directly supplied to the memory cell array and sense amplifier circuit through a switch. The cell array internal voltage may be applied to a bit line connected to a memory cell through a sense amplifier.
In further embodiments of the present invention, circuits are provided for supplying cell array power supply voltage in a semiconductor memory device. A power supply providing line is provided, the power supply providing line configured to directly supply a second power supply voltage, applied from external to the semiconductor memory device separately from a first power supply voltage, to a memory cell array and sense amplifier circuit as a cell array internal voltage for operation of the memory cell array and sense amplifier. The first power supply voltage is for use in core and peripheral circuits of the semiconductor memory device and the second power supply voltage is for use in a data output circuit of the semiconductor memory device.